1. Technical Field
The present invention relates to integrated circuits in general, and in particular to bi-stable integrated circuits. Still more particularly, the present invention relates to a single-event upset tolerant latch for sense amplifiers.
2. Description of the Prior Art
In certain environments, such as satellite orbital space, in which the level of radiation is relatively intense, electronic devices that utilize static random access memories (SRAMs) are more susceptible to single-event upsets (SEUs) or soft errors than they would have in terrestrial environments. These SEUs are typically caused by electron-hole pairs created by, and travelling along the path of, a single energetic particle as it passes through the memory cells of the SRAMs. Should the energetic particle generate a critical charge within a storage node of an SRAM cell, the logic state of the SRAM cell will be upset. Thus, the critical charge is the minimum amount of electrical charge required to change the logic state of the SRAM cell. By the same token, other circuits used in conjunction with SRAMs are also susceptible to SEUs. For example, one of such circuits are sense latches within sense amplifiers for SRAMs.
Referring now to the drawings and in particular to FIG. 1, there is illustrated a schematic diagram of a conventional sense latch that is commonly used in SRAMs. As shown, a sense latch 10 is constructed with two cross-coupled complementary metal oxide semiconductor (CMOS) inverters. The first inverter includes a p-channel transistor 11 connected in series with an n-channel transistor 12. The second inverter includes a p-channel transistor 13 connected in series with an n-channel transistor 14. The gates of transistors 11 and 12 are connected to the drains of transistors 13 and 14, and the gates of transistors 13 and 14 are connected to the drains of transistors 11 and 12. This arrangement of inverters is commonly referred to as cross-coupled inverters, and the two lines connecting the gates and the drains of the inverters are commonly referred to as cross-coupling lines. The drains of transistors 11, 12 and the gates of transistors 13, 14 are connected to a bitline BL. Similarly, the drains of transistors 13, 14 and the gates of transistors 11, 12 are connected to a bitline {overscore (BL)}. Both BL and {overscore (BL)} are connected to a column of SRAM cells for sensing a logical state of a specific SRAM cell, as it is well-known to those skilled in the art. The cross-coupled inverters are coupled to ground via an n-channel transistor 15 that can be controlled by a SET signal to the gate of transistor 15.
During operation, BL and {overscore (BL)} are equally charged to the positive power supply potential with the SET signal at the gate of transistor 15 held to ground potential. When an SRAM cell in the column above sense latch 10 is accessed, the SRAM cell begins to discharge either BL or {overscore (BL)} by a few hundred millivolts. At which time, the SET signal at the gate of transistor 15 is raised to the positive supply potential, causing conduction in the cross-coupled inverters to begin. The slight imbalance in potential on BL and {overscore (BL)} is amplified by the non-linear conduction behavior of the p-channel transistors at conduction threshold, causing a regenerative amplification to occur that causes either BL or {overscore (BL)} to be discharged all the way to ground potential in order to reflect the same logical as that of the SRAM cell. At this point, the SRAM cell may be disconnected from BL and {overscore (BL)} without changing the logical state of sense latch 10. If, however, an energetic atomic particle intersects any of the diffusion regions of BL or {overscore (BL)} that has remained in the positive logical state, the energetic atomic particle can transiently drives that node below the unity gain point of the inverters within sense latch 10, causing an indeterminate state after recovery from the transient. Such state may be of opposite polarity from the pre-transient state, signifying an SEU event has occurred.
Consequently, it would be desirable to provide an SEU tolerant sense latch.
In accordance with a preferred embodiment of the present invention, a single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series. The second set of dual-path inverters is coupled to the second set of isolation transistors, and the second set of dual-path inverters includes a fifth transistor connected to a sixth transistor in series along with a seventh transistor connected to an eighth transistor in series. The isolation transistor couples the first and second sets of dual-path inverters to ground.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.